dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
Bit Field
RSS<1:0>
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Description
FSS
Secure Segment Data RAM Code Protection
11= No Data RAM is reserved for Secure Segment
10= Small-sized Secure RAM
[(256 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
01= Medium-sized Secure RAM
[(2048 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
00= Large-sized Secure RAM
[(4096 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
where N = Number of bytes of RAM reserved for Boot Sector.
Note 1: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
2: If the defined Boot Segment size is greater than or equal to
the defined Secure Segment, then the Secure Segment size
selection has no effect and the Secure Segment is disabled.
SSS<2:0>
FSS
Secure Segment Program Memory Code Protection
111= No Secure Segment
110= Standard security, Small-sized Secure Program Flash
[Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in
other devices.]
101= Standard security, Medium-sized Secure Program Flash
[Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in
other devices.]
100= Standard security, Large-sized Secure Program Flash
[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in
other devices.]
011= No Secure Segment
010= High security, Small-sized Secure Program Flash
[Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in
other devices.]
001= High security, Medium-sized Secure Program Flash
[Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in
other devices.]
000= High security, Large-sized Secure Program Flash
[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in
other devices.]
[Note: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
SWRP
FSS
Secure Segment Program Memory Write Protection
1= Secure Segment program memory is not write-protected
0= Secure program memory is write-protected
[Note: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
DS70152D-page 42
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
