dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
GSS<1:0>
FGS
General Segment Code-Protect bit
11= Code protection is disabled
10= Standard security code protection is enabled
0x= Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202
and PIC24HJ12GP201/202. In all other devices, high security code
protection is enabled.
GWRP
IESO
FGS
General Segment Write-Protect bit
1= General Segment program memory is not write-protected
0= General Segment program memory is write-protected
FOSCSEL
Two-speed Oscillator Start-Up Enable bit
1= Start up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start up device with user-selected oscillator source
TEMP
FOSCSEL
FOSCSEL
Temperature Protection Enable bit
1= Temperature protection disabled
0= Temperature protection enabled
FNOSC<2:0>
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator
110= Reserved
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= Reserved
FCKSM<1:0>
IOL1WAY
FOSC
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Peripheral Pin Select Configuration
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
[Note: This bit is only present in the dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]
OSCIOFNC
FOSC
FOSC
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS crystal oscillator mode
01= XT crystal oscillator mode
00= EC (external clock) mode
FWDTEN
FWDT
Watchdog Enable bit
1= Watchdog always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect)
0= Watchdog enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
FWDT
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 43
MICROCHIP [ MICROCHIP ]
