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ATMEGA88-20AU 参数 Datasheet PDF下载

ATMEGA88-20AU图片预览
型号: ATMEGA88-20AU
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 8KB FLASH 32TQFP]
分类和应用: 时钟ATM异步传输模式PC微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer  
on Compare match (CTC) mode using OCR1A as TOP.  
The FOC1A/FOC1B bits are always read as zero.  
13.10.4 Timer/Counter1 – TCNT1H and TCNT1L  
Bit  
7
6
5
4
3
2
1
0
TCNT1[15:8]  
TCNT1[7:0]  
TCNT1H  
TCNT1L  
Read/Write  
Initial Value  
R/W  
R/W  
0
R/W  
0
R/W  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct  
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To  
ensure that both the high and low bytes are read and written simultaneously when the CPU  
accesses these registers, the access is performed using an 8-bit temporary High Byte Register  
(TEMP). This temporary register is shared by all the other 16-bit registers. See Section “13.2” on  
page 108.  
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-  
pare match between TCNT1 and one of the OCR1x Registers.  
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock  
for all compare units.  
13.10.5 Output Compare Register 1 A – OCR1AH and OCR1AL  
Bit  
7
6
5
4
3
2
1
0
OCR1A[15:8]  
OCR1A[7:0]  
OCR1AH  
OCR1AL  
Read/Write  
Initial Value  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0
R/W  
0
R/W  
0
0
0
0
0
0
13.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL  
Bit  
7
6
5
4
3
2
1
0
OCR1B[15:8]  
OCR1B[7:0]  
OCR1BH  
OCR1BL  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
R/W  
R/W  
0
R/W  
0
R/W  
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the  
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to  
generate a waveform output on the OC1x pin.  
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are  
written simultaneously when the CPU writes to these registers, the access is performed using an  
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other  
16-bit registers. See Section “13.2” on page 108.  
132  
ATmega48/88/168  
2545E–AVR–02/05  
 
 
 
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