欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第224页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第225页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第226页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第227页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第229页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第230页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第231页浏览型号ATMEGA16M1-15MZ的Datasheet PDF文件第232页  
Table 20-2. Analog Comparator 0 Negative Input Selection  
AC0M2  
AC0M1  
AC0M0  
Description  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
“Vref”/6.40  
“Vref”/3.20  
“Vref”/2.13  
“Vref”/1.60  
Bandgap (1.1V)  
DAC result  
Analog comparator negative input (ACMPM pin)  
Reserved  
20.4.2 Analog Comparator 1 Control Register – AC1CON  
Bit  
7
AC1EN  
R/W  
0
6
AC1IE  
R/W  
0
5
4
3
2
1
0
AC1IS1 AC1IS0 AC1ICE AC1M2 AC1M1 AC1M0 AC1CON  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
• Bit 7– AC1EN: Analog Comparator 1 Enable Bit  
Set this bit to enable the analog comparator 1.  
Clear this bit to disable the analog comparator 1.  
• Bit 6– AC1IE: Analog Comparator 1 Interrupt Enable bit  
Set this bit to enable the analog comparator 1 interrupt.  
Clear this bit to disable the analog comparator 1 interrupt.  
• Bit 5, 4– AC1IS1, AC1IS0: Analog Comparator 1 Interrupt Select bit  
These 2 bits determine the sensitivity of the interrupt trigger.  
The different setting are shown in Table 18-7.  
Table 20-3. Interrupt Sensitivity Selection  
AC1IS1  
AC1IS0  
Description  
0
0
1
1
0
1
0
1
Comparator Interrupt on output toggle  
Reserved  
Comparator interrupt on output falling edge  
Comparator interrupt on output rising edge  
• Bit 3– AC1ICE: analog comparator 1 Interrupt Capture Enable bit  
Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator event. The comparator output is in  
this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge  
select features of the Timer/Counter1 input capture interrupt. To make the comparator trigger the Timer/Counter1 input  
capture interrupt, the ICIE1 bit in the timer interrupt mask register (TIMSK1) must be set.  
In case ICES1 bit (Section 13.10.2 “Timer/Counter1 Control Register B – TCCR1B” on page 112) is set high, the rising edge  
of AC1O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to zero, it is the falling edge which is taken  
into account.  
Clear this bit to disable this function. In this case, no connection between the analog comparator and the input capture  
function exists.  
• Bit 2, 1, 0– AC1M2, AC1M1, AC1M0: analog comparator 1 Multiplexer register  
These 3 bits determine the input of the negative input of the analog comparator.  
The different setting are shown in Table 20-4 on page 229.  
228  
ATmega16/32/64/M1/C1 [DATASHEET]  
7647O–AVR–01/15  
 
 复制成功!