Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC noise
reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption. If the ADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is
advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result.
18.6.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 18-8 An analog source applied to ADCn is
subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined
resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used,
the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long
time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few
hundred k or less is recommended.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid
distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass
filter before applying the signals as inputs to the ADC.
Figure 18-8. Analog Input Circuitry
IIH
ADCn
1 to 100kΩ
IIL
CS/H = 14pF
VCC/2
18.6.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If
conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and
keep them well away from high-speed switching digital tracks.
2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an RC network (R = 10
max, C = 100nF).
3. Use the ADC noise canceler function to reduce induced noise from the CPU.
4. If any ADC port pins (PB[7:2], PC[7:4], PD[6:4], PE[2]) are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
18.6.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as
possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs using the
AMPxIS bit with both inputs unconnected (see Section 18.11.1 “Amplifier 0 control and status register – AMP0CSR” on page
218, see Section 18.11.2 “Amplifier 1 Control and Status Register – AMP1CSR” on page 219 and see Section 18.11.2
“Amplifier 1 Control and Status Register – AMP1CSR” on page 219). This offset residue can be then subtracted in software
from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced
below one LSB.
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ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
