Figure 18-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
ADSC
12
13
14
1
2
3
4
5
ADIF
ADCH
Sign and MSB of Result
LSB of Result
ADCL
Sample and
Hold
Conversion
Complete
MUX and REFS
Update
Table 18-1. ADC Conversion Time
Condition
Normal Conversion,
Single Ended
Auto Triggered
Conversion
First Conversion
Sample and Hold
(Cycles from Start of Conversion)
13.5
3.5
2
Conversion Time
(Cycles)
25
15.5
16
18.5 Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has
random access. This ensures that the channels and reference selection only takes place at a safe point during the
conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating
resumes in the last eight ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the second following rising CPU clock edge after ADSC is written. The user is thus advised not to write
new channel or reference selection values to ADMUX until two ADC clock cycle after ADSC is written.
If auto triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when
updating the ADMUX register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX register is changed in this
period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in
the following ways:
1. When ADATE or ADEN is cleared.
2. during conversion, with taking care of the trigger source event, when it is possible.
3. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
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ATmega16/32/64/M1/C1 [DATASHEET]
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