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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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18.5.1 ADC Input Channels  
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is  
selected:  
In single conversion mode, always select the channel before starting the conversion. The channel selection may be  
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion  
to complete before changing the channel selection.  
In free running mode, always select the channel before starting the first conversion. The channel selection may be  
changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first  
conversion to complete, and then change the channel selection. Since the next conversion has already started  
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new  
channel selection.  
In free running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not possible  
to use the free running mode, unless ADSC bit is set again by soft at the end of each conversion.  
Note:  
When The ADC and COMPARATOR share the same channel (possible configuration for AMP1+, AMP1- and  
AMP2-), up to revision B of ATmega32M1 the comparator is disconnected during the sampling of the ADC. For  
ATmega16/64 and ATmega32 revision C, the COMPARATOR is always connected.  
18.5.2 ADC Voltage Reference  
The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed  
VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF  
pin.  
AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal  
bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the  
ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and  
ground. VREF can also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant  
source, and only a capacitive load should be connected in a system.  
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options  
in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user  
may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference  
voltage source may be inaccurate, and the user is advised to discard this result.  
AREF pin is alternate function with ISRC current source output. When current source is selected, the AREF pin is not  
connected to the internal reference voltage network. See AREFEN and ISRCEN bits in Section 18.9.3 “ADC control and  
status register B– ADCSRB” on page 212.  
If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 26-6 on page  
280.  
18.6 ADC Noise Canceler  
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core  
and other I/O peripherals. The noise canceler can be used with ADC noise reduction and Idle mode. To make use of this  
feature, the following procedure should be used:  
Make sure the ADATE bit is reset.  
Make sure that the ADC is enabled and is not busy converting. Single conversion mode must be selected and the  
ADC conversion complete interrupt must be enabled.  
Enter ADC noise reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.  
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and  
execute the ADC conversion complete interrupt routine. If another interrupt wakes up the CPU before the ADC  
conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be  
generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is  
executed.  
ATmega16/32/64/M1/C1 [DATASHEET]  
203  
7647O–AVR–01/15  
 
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