93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
2.5
ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
low (TCSL).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
CHECK STATUS
CLK
DI
1
0
0
1
0
X
X
•••
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
VCC must be ≥ 4.5V for proper operation of ERAL.
TEC
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
TCSL
CS
CHECK STATUS
CLK
DI
1
0
0
1
0
X
X
•••
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TEC
2003 Microchip Technology Inc.
DS21749D-page 7
MICROCHIP [ MICROCHIP ]
