93XX46X/56X/66X/76X/86X
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
3.9
WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AAXX and 93LCXX devices, after the last data
bit is clocked into DI, the falling edge of CS initiates the
self-timed auto-erase and programming cycle. For
93CXX devices, the self-timed auto-erase and pro-
gramming cycle is initiated by the rising edge of CLK on
the last data bit. Clocking of the CLK pin is not neces-
sary after the device has entered the WRAL cycle. The
WRAL command does include an automatic ERAL
cycle for the device. Therefore, the WRAL instruction
does not require an ERALinstruction, but the chip must
be in the EWEN status.
VCC must be ≥ 4.5V for proper operation of WRAL.
Note:
For devices with PE functionality such as
the 93XX76C or 93XX86C, the write
sequence requires a logic high signal on
the PE pin prior to the rising edge of clock
on the last data bit.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
FIGURE 3-10:
WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES
TCSL
CS
CLK
0
0
1
X
1
0
•••
Dx
•••
x
D0
DI
TSV
TCZ
High-Z
Busy
DO
Ready
HIGH-Z
TWL
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 3-11:
WRAL TIMING FOR 93CXX DEVICES
TCSL
CS
CLK
0
0
1
X
1
0
•••
Dx
•••
DI
x
D0
TSV
TCZ
High-Z
Busy
DO
Ready
HIGH-Z
TWL
DS21929D-page 16
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
