93XX46X/56X/66X/76X/86X
4.0
PIN DESCRIPTIONS
TABLE 4-1:
Name
PIN DESCRIPTIONS
SOIC/PDIP/MSOP/
TSSOP/DFN
SOT-23
Function
CS
CLK
DI
1
2
3
4
5
5
4
3
1
2
Chip Select
Serial Clock
Data In
DO
Data Out
Ground
VSS
ORG
NC(1)
PE
Organization (93XX46C/56C/66C/76C/86C)
No connect on 93XXA/B devices
Program Enable (93XX76C/86C)
No connect on 93XXA/B devices
Power Supply
6
N/A
7
8
N/A
6
NC(1)
VCC
Note 1: With no internal connection, logic levels on NC pins are “don’t cares.”
After detection of a Start condition the specified number
4.1
Chip Select (CS)
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
4.3
Data In (DI)
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
4.4
Data Out (DO)
4.2
Serial Clock (CLK)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
This pin also provides Ready/Busy status information
during Erase and Write cycles. Ready/Busy status
information is available on the DO pin if CS is brought
high after being low for minimum Chip Select Low Time
(TCSL) and an erase or write operation has been
initiated.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to Clock High Time (TCKH) and
Clock Low Time (TCKL). This gives the controlling mas-
ter freedom in preparing opcode, address and data.
The Status signal is not available on DO, if CS is held
low during the entire Erase or Write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
Erase/Write cycle, the data line will be high to indicate
the device is ready.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
Note:
After the Read cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CLK cycles are not required during the self-timed Write
(i.e., auto Erase/Write) cycle.
© 2007 Microchip Technology Inc.
DS21929D-page 17
MICROCHIP [ MICROCHIP ]
