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93C465AT-E/MC 参数 Datasheet PDF下载

93C465AT-E/MC图片预览
型号: 93C465AT-E/MC
PDF下载: 下载PDF文件 查看货源
内容描述: 1K - 16K与Microwire兼容串行EEPROM [1K-16K Microwire Compatible Serial EEPROMs]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 38 页 / 703 K
品牌: MICROCHIP [ MICROCHIP ]
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93XX46X/56X/66X/76X/86X  
The DO pin indicates the Ready/Busy status of the  
device, if CS is brought high after a minimum of 250 ns  
low (TCSL).  
3.5  
ERASE ALL (ERAL)  
The Erase All (ERAL) instruction will erase the entire  
memory array to the logical ‘1’ state. The ERAL cycle  
is identical to the Erase cycle, except for the different  
opcode. The ERAL cycle is completely self-timed and  
commences at the falling edge of the CS, except on  
‘93CXX’ devices where the rising edge of CLK before  
the last data bit initiates the write cycle. Clocking of the  
CLK pin is not necessary after the device has entered  
the ERAL cycle.  
VCC must be 4.5V for proper operation of ERAL.  
Note:  
After the ERAL command is complete,  
issuing a Start bit and then taking CS low  
will clear the Ready/Busy status from DO.  
FIGURE 3-3:  
ERAL TIMING FOR 93AAXX AND 93LCXX DEVICES  
TCSL  
Check Status  
CS  
CLK  
DI  
1
0
0
1
0
X
X
•••  
TSV  
TCZ  
High-Z  
DO  
Busy  
Ready  
High-Z  
TEC  
Vcc must be 4.5V for proper operation of ERAL.  
FIGURE 3-4:  
ERAL TIMING FOR 93CXX DEVICES  
TCSL  
CS  
Check Status  
CLK  
1
0
0
1
0
X
X
•••  
DI  
TSV  
TCZ  
High-Z  
DO  
Busy  
Ready  
High-Z  
TEC  
DS21929D-page 12  
© 2007 Microchip Technology Inc.  
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