PIC12CE67X
TABLE 9-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
uuu1 0uuu
---- --0-
---- --u-
---- --u-
---- --u-
---- --u-
---- --u-
MCLR Reset during normal operation
MCLR Reset during SLEEP
000h
000h
WDT Reset during normal operation
WDT Wake-up from SLEEP
000h
PC + 1
(1)
Interrupt wake-up from SLEEP
PC + 1
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 9-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
11xx xxxx
---0 0000
0000 000x
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --0-
1000 00--
---- -000
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
INDF
TMR0
PCL
(2)
PC + 1
(3)
(3)
STATUS
FSR
000q quuu
uuuq quuu
uuuu uuuu
11uu uuuu
---0 0000
0000 000u
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --u-
uuuu uu--
---- -000
uuuu uuuu
11uu uuuu
---u uuuu
GPIO
PCLATH
INTCON
PIR1
(1)
uuuu uqqq
(4)
-q-- ----
(5)
ADCON0
OPTION
TRIS
uuuu uquu
uuuu uuuu
--uu uuuu
-u-- ----
---- --u-
uuuu uu--
---- -uuu
PIE1
PCON
OSCCAL
ADCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 9-5 for reset value for specific condition.
4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause
bit 6 = u.
5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause
bit 3 = u.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 51