ML2258
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Continued)
CONDITIONS
TYP
MIN (NOTE 4)
MAX
UNITS
NOTES
AC and Dynamic Performance Characteristics (Note 10)
t
ACQ
f
CLK
t
C
SNR
Sample and Hold Acquisition
Clock Frequency
Conversion Time
Signal to Noise Ratio
5
5
V
IN
= 51kHz, 5V sine.
f
CLK
= 10.24MHz
(f
SAMPLING
> 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of f
SAMPLING
V
IN
= 51kHz, 5V sine.
f
CLK
= 10.24MHz
(f
SAMPLING
> 150kHz). THD is sum
of 2, 3, 4, 5 harmonics relative to
fundamental
V
IN
= f
A
+ f
B
. f
A
= 49kHz, 2.5V sine.
f
B
= 47.8kHz, 2.5V sine,
f
CLK
= 10.24MHz
(f
SAMPLING
> 150kHz). IMD is (f
A
+ f
B
),
(f
A
– f
B
), (2f
A
+ f
B
), (2f
A
– f
B
), (f
A
+ 2f
B
),
(f
A
– 2f
B
) relative to fundamental
V
IN
= 0 to 50kHz. 5V sine relative
to 1kHz
6, 11
5
5
6, 12
5
5
5
6
6
t
1H, 0H
C
IN
C
OUT
Note 1:
Note 2:
Note 3:
Note
Note
Note
Note
Note
4:
5:
6:
7:
8:
4
100
67
47
10240
1/f
CLK
kHz
dB
67 + 250ns 1/f
CLK
THD
Total Harmonic Distortion
–60
dB
IMD
Intermodulation Distortion
–60
dB
FR
t
DC
t
EOC
t
WS
t
SS
t
WALE
t
S
t
H
t
H1, H0
Frequency Response
Clock Duty Cycle
End of Conversion Delay
Start Pulse Width
Start Pulse Setup Time
Address Latch Enable Pulse Width
Address Setup
Address Hold
Output Enable for DB0–DB7
Output Disable for DB0–DB7
Capacitance of Logic Input
Capacitance of Logic Outputs
0.1
40
8
50
60
8 + 250ns
dB
%
1/f
CLK
ns
ns
ns
ns
ns
100
50
200
100
ns
ns
ns
ns
pF
pF
Synchronous only
40
50
0
50
Figure 1, C
L
= 50pF
Figure 1, C
L
= 10pF
Figure 1, C
L
= 50pF
Figure 1, C
L
= 10pF
5
10
6
6
Note 9:
Note 10:
Note 11:
Note 12:
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
< V– or V
IN
> V+) the absolute value of current at that pin should be limited to 25mA or less.
–40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-
case test conditions.
Typicals are parametric norm at 25°C.
Parameter guaranteed and 100% production tested.
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
For –V
REF
• V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5V) can
cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an
absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage of 4.900V
DC
over temperature variations, initial tolerance and loading.
Leakage current is measured with the clock not switching.
C
L
= 50pF, timing measured at 50% point.
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.
The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,
start conversion will have an uncertainty of one clock pulse.
4
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
