KSZ8795CLX
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these
in their own ways.
3.4.6.1
Direction of Energy
The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, espe-
cially when this energy change may impact the level at which the system should re-enter to the normal power state.
3.4.6.2
Direction of Link-Up
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
3.4.6.3
Magic Packet
The Magic Packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF)
followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Since the magic packet is only scanned
for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer
protocol.
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable
of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the
LAN controller receives a Magic Packet frame, it will alert the system to wake up. Once the KSZ8795CLX has been
enabled for Magic Packet Detection in Port PME Control Mask Register Bit[2] in the PME indirect register, it scans all
incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a Magic
Packet frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as source address
(SA), destination address (DA), which may be the receiving station’s IEEE MAC address, or a multicast or broadcast
address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node, with no breaks
or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization
stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as
long as the 16 duplications of the IEEE address match the address of the machine to be awakened.
Example of Magic Packet:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scan-
ning for the data sequence (assuming an Ethernet frame):
DA - SA - TYPE - FF FF FF FF FF FF - 11 22 33 44 55 66 -11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66
- 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66
-MISC-CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or
an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node
at the frame’s destination. If the scans do not find the specific sequence shown above, it discards the frame and takes
no further action. If the KSZ8795CLX detects the data sequence, however, it then alerts the PC’s power management
circuitry (assert the PME pin) to wake-up the system.
3.4.7
INTERRUPT (INT_N/PME_N)
INT_N is an interrupt signal that is used to inform the external controller that there has been a status update in the
KSZ8795CLX interrupt status register. Bits [3:0] of Register 125 are the interrupt mask control bits to enable and disable
the conditions for asserting the INT_N signal. Bits [3:0] of Register 124 are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading those bits in the Register 124.
PME_N is an optional PME interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8795CLX interrupt status register. Bits [4] of Register 125 are the PME mask control bits to enable
and disable the conditions for asserting the PME_N signal. Bits [4] of Register 124 are the PME interrupt status bits to
indicate which PME interrupt conditions have occurred. The PME interrupt status Bit[4] is cleared after reading this bit
of the Register 124.
Additionally, the interrupt pins of INT_N and PME_N eliminate the need for the processor to poll the switch for status
change.
2016 Microchip Technology Inc.
DS00002112A-page 25
MICREL [ MICREL SEMICONDUCTOR ]
