KSZ8795CLX
- IGMP v1/v2/v3 Snooping for Multicast Packet
Filtering
- Supports IEEE P802.3az Energy Efficient
Ethernet (EEE) to Reduce Power Consump-
tion in Transceivers in LPI State Even
Though Cables are Not Removed
- QoS/CoS Packets Prioritization Support:
802.1p, DiffServ-Based and Re-Mapping of
802.1p Priority Field Per Port Basis on Four
Priority Levels
- Dynamic Clock Tree Control to Reduce
Clocking in Areas that are Not in Use
- IPv4/IPv6 QoS Support
- Low Power Consumption without Extra
Power Consumption on Transformers
- IPV6 Multicast Listener Discovery (MLD)
Snooping
- Voltages: Using External LDO Power Sup-
plies
- Programmable Rate Limiting at the Ingress
and Egress Ports on a Per Port Basis
- Analog VDDAT 3.3V or 2.5V
- Jitter-Free Per Packet Based Rate Limiting
Support
- VDDIO Support 3.3V, 2.5V, and 1.8V
- Low 1.2V Voltage for Analog and Digital Core
Power
- Tail Tag Mode (1 byte Added before FCS)
Support on Port 5 to Inform the Processor
which Ingress Port Receives the Packet
- WoL Support with Configurable Packet Con-
trol
- Broadcast Storm Protection with Percentage
Control (Global and Per Port Basis)
• Additional Features
- Single 25 MHz +50 ppm Reference Clock
Requirement
- 1K Entry Forwarding Table with 64 KB Frame
Buffer
- Comprehensive Programmable Two-LED
Indicator Support for Link, Activity, Full-/Half-
Duplex, and 10/100 Speed
- 4 Priority Queues with Dynamic Packet Map-
ping for IEEE 802.1P, IPV4 TOS (DIFF-
SERV), IPv6 Traffic Class, etc.
• Packaging and Environmental
- Supports WoL Using AMD’s Magic Packet
- VLAN and Address Filtering
- Commercial Temperature Range: 0°C to
+70°C
- Supports 802.1x Port-Based Security,
Authentication and MAC-Based Authentica-
tion via Access Control Lists (ACL)
- Industrial Temperature Range: –40°C to
+85°C
- Package Available in an 80-Pin LQFP, Lead-
Free (RoHS-Compliant) Package
- Provides Port-Based and Rule-Based ACLs
to Support Layer 2 MAC SA/DA Address,
Layer 3 IP Address and IP Mask, Layer 4
TCP/UDP Port Number, IP Protocol, TCP
Flag and Compensation for the Port Security
Filtering
- Supports Human Body Model (HBM) ESD
Rating of 5 kV
- 0.065 µm CMOS Technology for Lower
Power Consumption
- Ingress and Egress Rate Limit Based on Bit
per Second (bps) and Packet-Based Rate
Limiting (pps)
• Configuration Registers Access
- High-Speed SPI (4-Wire, up to 50 MHz) Inter-
face to Access All Internal Registers
- MII Management (MIIM, MDC/MDIO 2-Wire)
Interface to Access All PHY Registers per
Clause 22.2.4.5 of the IEEE 802.3 Specifica-
tion
- I/O Pin Strapping Facility to Set Certain Reg-
ister Bits from I/O Pins During Reset Time
- Control Registers Configurable On-the-Fly
• Power and Power Management
- Full-Chip Software Power-Down (All Register
Values are Not Saved and Strap-In value Will
Re-Strap after it Releases the Power-Down)
- Per-Port Software Power-Down
- Energy Detect Power-Down (EDPD), which
Disables the PHY Transceiver When Cables
are Removed
2016 Microchip Technology Inc.
DS00002112A-page 2
MICREL [ MICREL SEMICONDUCTOR ]
