Micrel, Inc.
KSZ8041NL
Pin Description
Pin Number
1
2
3
4
5
6
7
8
Pin Name
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
TX+
XO
Type
Gnd
P
P
I/O
I/O
I/O
I/O
O
(1)
Pin Function
Ground
1.8V analog V
DD
3.3V analog V
DD
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode is selected.
9
XI /
REFCLK
I
Crystal / Oscillator / External Clock Input
MII Mode:
RMII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
50MHz +/-50ppm (oscillator, or external clock only)
10
11
12
13
REXT
MDIO
MDC
RXD3 /
PHYAD0
I/O
I/O
I
Ipu/O
Set physical transmit output current
Pull-down this pin with a 6.49KΩ resistor to ground.
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MII Mode:
Config Mode:
Receive Data Output[3]
(2)
/
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[2]
(2)
14
RXD2 /
PHYAD1
Ipd/O
MII Mode:
Config Mode:
/
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[1]
Receive Data Output[1]
(2)
(3)
15
RXD1 /
RXD[1] /
PHYAD2
Ipd/O
MII Mode:
RMII Mode:
Config Mode:
/
/
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[0]
Receive Data Output[0]
(2)
(3)
16
RXD0 /
RXD[0] /
DUPLEX
Ipu/O
MII Mode:
RMII Mode:
Config Mode:
/
/
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
Receive Data Valid Output /
Carrier Sense/Receive Data Valid Output /
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
Receive Clock Output
17
18
VDDIO_3.3
RXDV /
CRSDV /
CONFIG2
P
Ipd/O
3.3V digital V
DD
MII Mode:
RMII Mode:
Config Mode:
19
RXC
O
MII Mode:
October 2006
9
M9999-102406-1.0
MICREL [ MICREL SEMICONDUCTOR ]
