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KSZ8041NL 参数 Datasheet PDF下载

KSZ8041NL图片预览
型号: KSZ8041NL
PDF下载: 下载PDF文件 查看货源
内容描述: 10BASE-T / 100BASE-TX物理层收发器 [10Base-T/100Base-TX Physical Layer Transceiver]
分类和应用:
文件页数/大小: 45 页 / 601 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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Micrel, Inc.  
KSZ8041NL  
List of Figures  
Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................15  
Figure 2. Typical Straight Cable Connection .......................................................................................................................20  
Figure 3. Typical Crossover Cable Connection ...................................................................................................................21  
Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode ...................................................................................22  
Figure 5. 50MHz Oscillator Reference Clock for RMII Mode...............................................................................................22  
Figure 6. KSZ8041NL Power and Ground Connections......................................................................................................23  
Figure 7. MII SQE Timing (10Base-T) .................................................................................................................................33  
Figure 8. MII Transmit Timing (10Base-T)...........................................................................................................................34  
Figure 9. MII Receive Timing (10Base-T)............................................................................................................................35  
Figure 10. MII Transmit Timing (100Base-TX).....................................................................................................................36  
Figure 11. MII Receive Timing (100Base-TX)......................................................................................................................37  
Figure 12. RMII Timing – Data Received from RMII............................................................................................................38  
Figure 13. RMII Timing – Data Input to RMII .......................................................................................................................38  
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................39  
Figure 15. MDC/MDIO Timing..............................................................................................................................................40  
Figure 16. Reset Timing.......................................................................................................................................................41  
Figure 17. Recommended Reset Circuit..............................................................................................................................42  
Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output......................................................42  
Figure 19. Reference Circuits for LED Strapping Pins.........................................................................................................43  
October 2006  
6
M9999-102406-1.0  
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