W78M32VP-XBX
multiple write buffer programming operations on the same write
buffer address range without intervening erases.
Definitions shows the address and data requirements for the chip
erase command sequence.
Use of the write buffer is strongly recommended for programming
when multiple words are to be programmed.
When the Embedded Erase algorithm is complete, that sector
returns to the read mode and addresses are no longer latched.
The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for
information on these status bits.
SECTOR ERASE
The sector erase function erases one or more sectors in the
memory array. (See Table 39 and Figure 6.) The device does not
require the system to preprogram a sector prior to erase. The
Embedded Erase algorithm automatically programs and verifies the
entire memory to an all zero data pattern prior to electrical erase.
After a successful sector erase, all locations within the erased
sector contain FFFFh. The system is not required to provide any
controls or timings during these operations.
The Unlock Bypass feature allows the host system to send program
commands to the Flash device without first writing unlock cycles
within the command sequence. See Unlock Bypass Section for
details on the Unlock Bypass function.
Any commands written during the chip erase operation are ignored.
However, note that a hardware reset immediately terminates the
erase operation. If that occurs, the chip erase command sequence
should be reinitiated once that sector has returned to reading array
data, to ensure the entire array is properly erased.
After the command sequence is written, a sector erase time-out
of no less than tSEA occurs. During the timeout period, additional
sector addresses may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional
cycles must be less than 50 μs. Any sector erase address and
command following the exceeded time-out (50μs) may or may
not be accepted. Any command other than Sector Erase or Erase
Suspend during the time-out period resets that sector to the read
mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out. The time-out begins from the rising edge of
the final WE# pulse in the command sequence.
ERASE SUSPEND/ERASE RESUME
COMMANDS
The Erase Suspend command allows the system to interrupt a
sector erase operation and then read data from, or program data to,
any sector not selected for erasure. The sector address is required
when writing this command. This command is valid only during the
sector erase operation, including the minimum tSEAtime-out period
during the sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase operation.
When the Embedded Erase algorithm is complete, the sector
returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by
reading DQ7 or DQ6/DQ2 in the erasing sector. Refer to Section
write operation status section for information on these status bits.
When the Erase Suspend command is written during the sector
erase operation, the device requires a maximum of 20 μs (5 μs
typical) to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and suspends
the erase operation.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase command
sequence should be reinitiated once that sector has returned to
reading array data, to ensure the sector is properly erased.
After the erase operation has been suspended, the device enters
the erase-suspend-read mode. The system can read data from or
program data to any sector not selected for erasure. (The device
“erase suspends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces status
information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or
is erase-suspended.
The Unlock Bypass feature allows the host system to send program
commands to the Flash device without first writing unlock cycles
within the command sequence. See Unlock Bypass Section for
details on the Unlock Bypass function.
After an erase-suspended program operation is complete, the
device returns to the erase-suspend-read mode. The system can
determine the status of the program operation using write operation
status bits, just as in the standard program operation.
Figure 6 illustrates the algorithm for the erase operation. Refer
to Erase and Programming Performance Section for parameters
and timing diagrams.
In the erase-suspend-read mode, the system can also issue the
Autoselect command sequence. Refer to Write Buffer Programming
Section and the Autoselect Section.
CHIP ERASE COMMAND SEQUENCE
Chip erase is a six-bus cycle operation as indicated by Table
39. These commands invoke the Embedded Erase algorithm,
which does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms and
verifies the entire memory to an all zero data pattern prior to
electrical erase. After a successful chip erase, all locations of
the chip contain FFFFh. The system is not required to provide
any controls or timings during these operations. The Command
To resume the sector erase operation, the system must write the
Erase Resume command. The address of the erase-suspended
sector is required when writing this command. Further writes of the
Resume command are ignored.Another Erase Suspend command
can be written after the chip has resumed erasing.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
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