W3E32M64S-XSBX
White Electronic Designs
Document Title
32M x 64 DDR SDRAM Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Initial Release
January 2004
June 2005
Advanced
Changes (Pg. 1, 6, 10, 11, 12, 15, 16, 17)
1.1 Change status to Preliminary
Preliminary
1.2 Change maximum storage temperature to 125°C
1.3 Add 333Mbs/166MHz speed grade
1.4 Change typical weight to 1.5g
1.5 Add thermal resistance values
1.6 PCN04019 — Change maximum package body thickness
to 2.56mm
Rev 2
Changes (Pg. 1 - 17)
September 2005
Final
2.1 Change status to Final
2.2 Change 333Mbs CAS latency to 133/166 for Military
Temperature and 166/166 for Industrial Temerature.
2.3 ICC1 Burst Length change from 2 to 4
2.4 ICCS; TREFC = TRFC (Min) correction
2.5 Refresh to refresh command interval at Military
temperature tREFC = 35μs, tREFI = 3.9μs
2.6 Added AC Input Operating Conditions Table
2.7 Note number updates page 11, 12, 15
2.8 Data rate corrected form MHz to Mbs
2.9 Note 48 removed (Duplicate)
Rev 3
Rev 4
Changes (Pg. 3)
June 2006
June 2006
Final
Final
3.1 Correction to pin out
Changes (Pg. 1, 11, 15)
4.1 Correction of ViL Min
4.2 Added note on solder ball metallurgy
Rev 5
Changes (Pg. 1, 10, 17)
July 2006
Final
5.1 Update thermal resistance values to typical
January 2008
Rev. 6
17
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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