W3E32M64S-XSBX
White Electronic Designs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1-5, 14-17, 33)
333 Mbs CL 3 (53) 266 Mbs CL 2.5
266 Mbs CL2.5 200 Mbs CL2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Parameter
Symbol
tAC
tCH
Min
-0.70
0.45
0.45
6
Max
+0.70
0.55
0.55
13
Min
-0.75
0.45
0.45
Max
+0.75
0.55
Min
-0.8
0.45
0.45
Max
+0.8
0.55
0.55
Min
-0.8
0.45
0.45
Max
+0.8
0.55
0.55
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
μs
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
tCL
0.55
CL = 3 (45, 51, 53)
CL = 2.5 (45, 51)
CL = 2 (45, 51)
tCK (3)
tCK (2.5)
tCK (2)
tDH
7.5
10
13
13
7.5
10
13
13
8
10
13
13
10
13
13
15
Clock cycle time
DQ and DM input hold time relative to DQS (26, 31)
0.45
0.45
1.75
-0.6
0.35
0.35
0.5
0.5
1.75
-0.75
0.35
0.35
0.6
0.6
2
-0.8
0.35
0.35
0.6
0.6
2
-0.8
0.35
0.35
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
+0.6
+0.75
+0.8
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
0.45
1.25
0.5
1.25
0.6
1.25
0.6
1.25
0.75
0.2
0.2
0.75
0.2
0.2
0.75
0.2
0.2
0.75
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
+0.70
+0.75
+0.8
+0.8
tLZ
-0.70
0.75
0.75
0.8
0.8
12
tHP-tQHS
0.55
42
15
60
72
15
-0.75
0.90
0.90
1
1
15
-0.8
1.1
1.1
1.1
1.1
-0.8
1.1
1.1
1.1
1.1
tIH
F
tIS
F
tIH
S
tIS
S
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
16
tHP-tQHS
16
tHP-tQHS
tHP-tQHS
0.75
120,000
1
1
70,000
40
20
65
75
20
20
0.9
0.4
15
0.25
0
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
15
0.9
0.4
12
0.25
0
0.4
15
1
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
REFRESH to REFRESH command interval (23) (commercial and
Industrial)
0.6
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
tWTR
NA
tREFC
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
70.3
70.3
70.3
70.3
REFRESH to REFRESH command interval (Military temperature)
Average periodic refresh interval (23) (commercial and Industrial)
Average periodic refresh interval (Military temperature)
Terminating voltage delay to VDD
tREFC
tREFI
tREFI
tVTD
35
7.8
3.9
35
7.8
3.9
35
7.8
3.9
35
7.8
3.9
μs
μs
μs
ns
0
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
200
75
200
80
200
80
200
ns
tCK
January 2008
Rev. 6
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
