26 Instruction Set
The 80C51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes
for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides
extensive support for one-bit variables as a separate data type, allowing direct bit manipulation in control and
logic systems that require Boolean processing.
The MPC82G516A instruction set is fully compatible with those of the 80C51 except the execution time, i.e., the
number of clock cycles required to execute an instruction. The shortest execution time is just one clock cycle and
the longest is 7 clock cycles.
Addressing Modes
The addressing modes in the 80C51 instruction set are as follows:
Direct Addressing
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM
and SFRs can be directly addressed.
Indirect Addressing
In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the
selected bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit “data
pointer” register, DPTR.
Register Instructions
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-
bit register specification within the opcode of the instruction. Instructions that access the registers this way are
code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select
bits in the PSW register.
Register-Specific Instructions
Some instructions are specific to a certain register. For example, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that.
Instructions that refer to the Accumulator as A assemble as accumulator specific opcodes.
Immediate Constants
The value of a constant can follow the opcode in Program Memory. For example, “MOV A, #100” loads the
Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H.
Indexed Addressing
Only program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode
is intended for reading look-up tables in Program Memory A 16-bit base register (either DPTR or the Program
Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address
of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer. Another type
of indexed addressing is used in the “case jump” instruction. In this case the destination address of a jump
instruction is computed as the sum of the base pointer and the Accumulator data.
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MPC82G516A Data Sheet
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