26.2 Logic Operations
Execution
Clock Cycles
Mnemonic
Description
Byte
LOGIC OPERATIONS
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rn
AND register to ACC
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
3
3
2
4
4
2
3
3
2
4
4
2
3
3
2
4
4
1
2
1
1
1
1
1
A,direct
A,@Ri
AND direct byte to ACC
AND indirect RAM to ACC
AND immediate data to ACC
AND ACC to direct byte
A,#data
direct,A
direct,#data
A,Rn
AND immediate data to direct byte
OR register to ACC
A,direct
A,@Ri
OR direct byte to ACC
OR indirect RAM to ACC
A,#data
direct,A
direct,#data
A,Rn
OR immediate data to ACC
OR ACC to direct byte
OR immediate data to direct byte
Exclusive-OR register to ACC
Exclusive-OR direct byte to ACC
Exclusive-OR indirect RAM to ACC
Exclusive-OR immediate data to ACC
Exclusive-OR ACC to direct byte
Exclusive-OR immediate data to direct byte
Clear ACC
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
Complement ACC
A
Rotate ACC Left
RLC
RR
A
Rotate ACC Left through the Carry
Rotate ACC Right
A
RRC
SWAP
A
Rotate ACC Right through the Carry
Swap nibbles within the ACC
A
MEGAWIN
MPC82G516A Data Sheet
124
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
