欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX29LV320ATTC-90G 参数 Datasheet PDF下载

MX29LV320ATTC-90G图片预览
型号: MX29LV320ATTC-90G
PDF下载: 下载PDF文件 查看货源
内容描述: 32M - BIT [ 4M ×8 / 2M ×16 ]单电压3V仅限于Flash存储器 [32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 60 页 / 604 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第11页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第12页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第13页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第14页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第16页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第17页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第18页浏览型号MX29LV320ATTC-90G的Datasheet PDF文件第19页  
MX29LV320AT/B  
WRITE PULSE "GLITCH" PROTECTION  
Noise pulses of less than 5ns (typical) on OE, CE or WE  
will not initiate a write cycle.  
LOGICAL INHIBIT  
Writing is inhibited by holding any one of OE =VIL, CE =  
VIH or WE = VIH. To initiate a write cycle CE and WE  
must be a logical zero while OE is a logical one.  
POWER-UP SEQUENCE  
The MX29LV320AT/B powers up in the Read only mode.  
In addition, the memory contents may only be altered  
after successful completion of the predefined command  
sequences.  
POWER-UP WRITE INHIBIT  
IfWE=CE=VIL and OE=VIH during power up, the device  
does not accept commands on the rising edge of WE.  
The internal state machine is automatically reset to the  
read mode on power-up.  
POWER SUPPLY DECOUPLING  
In order to reduce power switching effect, each device  
should have a 0.1uF ceramic capacitor connected be-  
tween itsVCC and GND.  
SOFTWARE COMMAND DEFINITIONS  
Device operations are selected by writing specific ad-  
dress and data sequences into the command register.  
Writing incorrect address and data values or writing them  
in the improper sequence will reset the device to the  
read mode. Table 3 defines the valid register command  
sequences. Note that the Erase Suspend (B0H) and  
Erase Resume (30H) commands are valid only while the  
Sector Erase operation is in progress. Either of the two  
reset command sequences will reset the device (when  
applicable).  
All addresses are latched on the falling edge of WE or  
CE, whichever happens later.All data are latched on ris-  
ing edge of WE or CE, whichever happens first.  
P/N:PM1008  
REV. 1.1, MAY 28, 2004  
15  
 复制成功!