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MX29LV320ATTC-90G 参数 Datasheet PDF下载

MX29LV320ATTC-90G图片预览
型号: MX29LV320ATTC-90G
PDF下载: 下载PDF文件 查看货源
内容描述: 32M - BIT [ 4M ×8 / 2M ×16 ]单电压3V仅限于Flash存储器 [32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 60 页 / 604 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29LV320AT/B  
Sector Erase operation. When the Erase Suspend com-  
mand is issued during the sector erase operation, the  
device requires a maximum 20us to suspend the sector  
erase operation.However,When the Erase Suspend com-  
mand is written during the sector erase time-out, the  
device immediately terminates the time-out period and  
suspends the erase operation. After this command has  
been executed, the command register will initiate erase  
suspend mode. The state machine will return to read  
mode automatically after suspend is ready. At this time,  
state machine only allows the command register to re-  
spond to the Erase Resume, program data to, or read  
data from any sector not selected for erasure. The sys-  
tem can use Q7, or Q6 and Q2 together, to determine if  
a sector is actively erasing or is erase-suspended.  
SECTOR ERASE COMMANDS  
The device does not require the system to entirely  
pre-program prior to executing the Automatic Set-up  
Sector Erase command and Automatic Sector Erase  
command. Upon executing the Automatic Sector  
Erase command, the device will automatically  
program and verify the sector(s) memory for an all-  
zero data pattern. The system is not required to  
provide any control or timing during these operations.  
When the sector(s) is automatically verified to  
contain an all-zero pattern, a self-timed sector erase  
and verify begin. The erase and verify operations are  
complete when the data on Q7 is "1" and the data on  
Q6 stops toggling for two consecutive read cycles, at  
which time the device returns to the Read mode. The  
system is not required to provide any control or timing  
during these operations.  
The system can determine the status of the program  
operation using the Q7 or Q6 status bits, just as in the  
standard program operation. After an erase-suspend pro-  
gram operation is complete, the system can once again  
read array data within non-suspended blocks.  
When using the Automatic Sector Erase algorithm,  
note that the erase automatically terminates when  
adequate erase margin has been achieved for the  
memory array (no erase verification command is  
required). Sector erase is a six-bus cycle operation.  
There are two "unlock" write cycles. These are  
followed by writing the set-up command 80H. Two  
more "unlock" write cycles are then followed by the  
sector erase command 30H. The sector address is  
latched on the falling edge of WE or CE, whichever  
happens later , while the command(data) is latched on  
the rising edge of WE or CE, whichever happens first.  
Sector addresses selected are loaded into internal  
register on the sixth falling edge of WE or CE,  
whichever happens later. Each successive sector  
load cycle started by the falling edge of WE or CE,  
whichever happens later must begin within 50us from  
the rising edge of the preceding WE or CE, whichever  
happens first. Otherwise, the loading period ends and  
internal auto sector erase cycle starts. (Monitor Q3 to  
determine if the sector erase timer window is still  
open, see section Q3, Sector Erase Timer.) Any  
command other than Sector Erase(30H) or Erase  
Suspend(B0H) during the time-out period resets the  
device to read mode.  
ERASE RESUME  
This command will cause the command register to clear  
the suspend state and return back to Sector Erase mode  
but only if an Erase Suspend command was previously  
issued. Erase Resume will not have any effect in all  
other conditions. Another Erase Suspend command can  
be written after the chip has resumed erasing.  
ERASE SUSPEND  
This command only has meaning while the state ma-  
chine is executing Automatic Sector Erase operation,  
and therefore will only be responded during Automatic  
P/N:PM1008  
REV. 1.1, MAY 28, 2004  
19  
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