MX29LV320AT/B
verifies the programmed cell margin. Table 3 shows the
address and data requirements for the byte/word program
command sequence.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6, or RY/
BY. See "Write Operation Status" for information on these
status bits.
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H, or
the sector erase command 30H.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading
array data, to ensure data integrity.
The MX29LV320AT/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of A7H/A8H for MX29LV320AT/B.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may cause the
device to set Q5 to "1" ,” or cause the Data Polling
algorithm to indicate the operation was successful.
TABLE 4. SILICON ID CODE
Pins
A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacturecode
VIL VIL
VIH VIL
VIH VIL
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
C2H
Device code for MX29LV320AT
Device code for MX29LV320AB
22A7H
22A8H
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
AUTOMATIC CHIP/SECTOR ERASE COMMAND
The device does not require the system to preprogram
prior to erase.The Automatic Erase algorithm automati-
cally preprograms and verifies the entire memory for an
all zero data pattern prior to electrical erase.The system
is not required to provide any controls or timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
The system can determine the status of the erase op-
eration by using Q7, Q6, Q2, or RY/BY. See "Write Op-
eration Status" for information on these status bits.When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hard-ware reset
during the chip erase operation immediately terminates
the operation.The Chip Erase command sequence should
Figure 5 illustrates the algorithm for the erase opera-tion.
See the Erase/Program Operations tables in "AC Char-
acteristics" for parameters, and to Figure 4 for timing
diagrams.
P/N:PM1008
REV. 1.1, MAY 28, 2004
18
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