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MX29LV160BBXBC-90 参数 Datasheet PDF下载

MX29LV160BBXBC-90图片预览
型号: MX29LV160BBXBC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ 2Mx8 / 1Mx16 ] CMOS单电压3V仅限于Flash存储器 [16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 存储
文件页数/大小: 63 页 / 762 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29LV160BT/BB  
CAPACITANCE TA = 25oC, f = 1.0 MHz  
SYMBOL  
CIN1  
PARAMETER  
MIN.  
TYP  
6
MAX.  
7.5  
9
UNIT  
pF  
CONDITIONS  
VIN = 0V  
Input Capacitance  
Control Pin Capacitance  
Output Capacitance  
CIN2  
7.5  
8.5  
pF  
VIN = 0V  
COUT  
12  
pF  
VOUT = 0V  
Table 9. DC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 2.7V~3.6V  
Symbol PARAMETER  
MIN.  
TYP  
MAX.  
± 1  
35  
± 1  
16  
4
UNIT  
uA  
CONDITIONS  
ILI  
Input Leakage Current  
VIN = VSS to VCC, VCC=VCC max  
VCC=VCC max; A9=12.5V  
VOUT = VSS to VCC, VCC=VCC max  
ILIT  
ILO  
ICC1  
A9 Input Leakage Current  
Output Leakage Current  
VCC Active Read Current  
uA  
uA  
9
2
mA  
mA  
mA  
mA  
mA  
uA  
CE=VIL, OE=VIH  
(Byte Mode)  
@5MHz  
@1MHz  
@5MHz  
@1MHz  
9
16  
4
CE=VIL, OE=VIH  
(Word Mode)  
2
ICC2  
ICC3  
ICC4  
VCC Active write Current  
VCC Standby Current  
VCC Standby Current  
During Reset (See Conditions)  
Automatic sleep mode  
Input Low Voltage (Note 1)  
Input High Voltage  
20  
0.2  
0.2  
30  
5
CE=VIL, OE=VIH, WE=VIL  
CE; RESET=VCC ± 0.3V  
RESET=VSS ± 0.3V  
5
uA  
ICC5  
VIL  
0.2  
5
uA  
V
VIH=VCC ± 0.3V;VIL=VSS ± 0.3V  
-0.5  
0.8  
VIH  
VID  
0.7xVCC  
VCC+ 0.3  
V
Voltage for Automatic  
Select and Temporary  
Sector Unprotect  
11.5  
12.5  
0.45  
V
V
VCC=3.3V  
VOL  
Output Low Voltage  
Output High Voltage (TTL)  
Output High Voltage  
(CMOS)  
IOL = 4.0mA, VCC= VCC min  
IOH = -2mA, VCC=VCC min  
IOH = -100uA, VCC min  
VOH1  
VOH2  
0.85xVCC  
VCC-0.4  
VLKO  
Low VCC Lock-out  
Voltage  
1.4  
2.1  
V
NOTES:  
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.  
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.  
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns  
If VIH is over the specified maximum value, read operation cannot be guaranteed.  
3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.  
P/N:PM1041  
REV. 1.2, JUL. 01, 2004  
22  
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