R
MX29LV160BT/BB
Q3
POWER SUPPLY DECOUPLING
Sector Erase Timer
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween itsVCC and GND.
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
andToggle Bit are valid after the initial sector erase com-
mand sequence.
POWER-UP SEQUENCE
The MX29LV160BT/BB powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system.TheTempo-
rary Sector Unprotect mode is activated by setting the
RESET pin toVID (11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin. All the previously protected sectors are pro-
tected again.
DATA PROTECTION
SECTOR PROTECTION
The MX29LV160BT/BB is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting fromVCC power-up and power-down tran-
sition or system noise.
The MX29LV160BT/BB features hardware sector pro-
tection. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE (suggestVID = 12V). Program-
ming of the protection circuitry begins on the falling edge
of the WE pulse and is terminated on the rising edge.
Please refer to sector protect algorithm and waveform.
To verify programming of the protection circuitry, the pro-
gramming equipment must forceVID on address pin A9
( with CE and OE atVIL andWE atVIH). When A1=VIH,
A0=VIL, A6=VIL, it will produce a logical "1" code at
device output Q0 for a protected sector. Otherwise the
device will produce 00H for the unprotected sector. In
this mode, the addresses, except for A1, are don't care.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes. (Read Silicon ID)
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE orWE
will not initiate a write cycle.
LOGICAL INHIBIT
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM1041
REV. 1.2, JUL. 01, 2004
19
Macronix [ MACRONIX INTERNATIONAL ]
