MX25L3205A
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write
Enable(WREN)instructionmustbedecodedandexecutedtosettheWriteEnableLatch(WEL)bitinadvance.TheWRSR
instructioncanchangethevalueofBlockProtect(BP2, BP1, BP0)bitstodefinetheprotectedareaofmemory(asshown
in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write
Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is
entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data
on SI-> CS# goes high. (see Figure 16)
The WRSR instruction has no effect on b6, b5, b1, b0 of the status register for.
TheCS#mustgohighexactlyatthebyteboundary;otherwise, theinstructionwillberejectedandnotexecuted. Theself-
timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,
and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 4. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP2
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
Software protection
mode(SPM)
The protected area cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP2 of
status register bits cannot be
changed
Hardware protection
mode (HPM)
The protected area cannot
be program or erase.
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
Astheabovetableshowing, thesummaryoftheSoftwareProtectedMode(SPM)andHardwareProtectedMode(HPM).
Software Protected Mode (SPM):
-
WhenSRWDbit=0,nomatterWP#isloworhigh,theWRENinstructionmaysettheWELbitandcanchangethevalues
of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode
(SPM).
-
WhenSRWDbit=1andWP#ishigh,theWRENinstructionmaysettheWELbitcanchangethevaluesofSRWD, BP2,
BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM)
P/N:PM1243
REV. 1.2, NOV. 06, 2006
12
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