MX25L3205A
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The
difference of SPI mode 0 and mode 3 is shown as Figure 3.
5. Forthefollowinginstructions:RDID,RDSR,READ,FAST_READ,RES,andREMS-theshifted-ininstructionsequence
is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, Parallel Mode, SE, CE, PP, EN4K, EX4K, RDP and DP the CS# must go high
exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand
not affect the current operation of Write Status Register, Program, Erase.
Figure 3. SPI Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(SPI mode 0)
(SPI mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is
supported.
P/N:PM1243
REV. 1.2, NOV. 06, 2006
9
Macronix [ MACRONIX INTERNATIONAL ]
