欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX25L4006EPI-12G 参数 Datasheet PDF下载

MX25L4006EPI-12G图片预览
型号: MX25L4006EPI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 串行外设接口兼容--mode 0和模式3 [Serial Peripheral Interface compatible --Mode 0 and Mode 3]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 52 页 / 1532 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX25L4006EPI-12G的Datasheet PDF文件第13页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第14页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第15页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第16页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第18页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第19页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第20页浏览型号MX25L4006EPI-12G的Datasheet PDF文件第21页  
MX25L4006E  
The sequence is shown as Figure 21.  
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte  
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-  
ecuted.  
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in  
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the  
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the  
page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.  
(12) Deep Power-down (DP)  
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-  
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode  
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-  
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep  
power-down mode. It's different from Standby mode.  
The sequence is shown as Figure 22.  
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)  
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-  
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby  
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction  
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay  
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.  
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)  
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip  
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the  
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in  
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip  
Select (CS#) must remain High for at least tRES2(max), as specified in Table 7. Once in the Stand-by Power mode,  
the device waits to be selected, so that it can receive, decode and execute instructions.  
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID  
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,  
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,  
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/  
write cycle in progress.  
The sequence is shown as Figure 23 and Figure 24.  
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-  
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously  
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in  
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least  
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute  
instruction.  
P/N: PM1576  
REV. 1.3, FEB. 10, 2012  
17