MX25L12845E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1-1.
For high performance (Double Transfer Rate Read serial mode), data is latched on both rising and falling edge
of clock and data shifts out on both rising and falling edge of clock as Figure 1-2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,FASTDTRD,
2DTRD, 4DTRD, RDBLOCK, PRLCR, RES, REMS, REMS2, REMS4 and REMS4D the shifted-in instruction
sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For
the following instructions: WREN, WRDI, Parallel Mode WRSR, SE, BE, BE32K, CE, PP, CP, 4PP, RDP, DP,
WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte
boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1-1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)
data
in
data
in
data data
out out
CPOL CPHA
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
P/N: PM1428
REV. 0.06, MAR. 05, 2009
13
Macronix [ MACRONIX INTERNATIONAL ]
