MX25L12845E
Table 2. Protected Area Sizes
Status bit
Protection Area
BP0 128Mb
BP3
1
BP2
1
BP1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
All
All
All
All
All
All
All
All
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
Upper half (hundrend and twenty-eight blocks: 128 to 255)
Upper quarter (sixty-four blocks: 192 to 255)
Upper eighth (thirty-two blocks: 224 to 255)
Upper sixteenth (sixteen blocks: 240 to 255)
Upper 32nd (eight blocks: 248 to 255)
Upper 64th (four blocks: 252 to 255)
Upper 128th (two blocks: 254 and 255)
None
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxxFFF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
P/N: PM1428
REV. 0.06, MAR. 05, 2009
11
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