MX25L12835F
9-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 16. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 17. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
N
SCLK
SIO[3:0]
05h
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
P/N: PM1795
REV. 1.0, OCT. 23, 2012
27
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