MX25L12835F
9-8. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Reg-
ister data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 18. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
15h
Configuration register Out
Configuration register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 19. Read Configuration Register (RDCR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
N
0
1
2
3
4
5
6
7
SCLK
SIO[3:0]
15h
H0 L0 H0 L0 H0 L0
H0 L0
MSB
LSB
Config. Byte Config. Byte Config. Byte
Config. Byte
P/N: PM1795
REV. 1.0, OCT. 23, 2012
28
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