MX10L8050X
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLHLL
TWHLH
PSEN
TLLWL
TWLWH
WR
TWHQX
TAVLL
TQVWX
TLLAX
TQVWH
A0-A7 FROM
INSTR. IN
PORT 0
PORT 2
DATA OUT
A0-A7 FROM RI OR DPL
PCL
TAVWL
A8-A15 FROM PCH
P2.0-P2.7 OR A8-A15 FROM DPH
SHIFT REGISTER MODE TIMING WAVEFORMS
2
5
8
1
4
7
0
3
6
INSTRUCTION
ALE
TXLXL
CLOCK
TXHQX
TQVXH
0
OUTPUT DATA
6
3
1
2
4
5
7
WRITE TO SBUF
TXHDV
TXHDX
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
P/N:PM0803
REV. 0.0, APR. 23, 2001
12