MX10L8050X
External clock drive XTAL
SYMBOL
PARAMETER
VARIABLE CLOCK
UNIT
MIN
1.2
63
20
20
-
MAX
fCLK
clock frequency
clock period
16 (tbf.)
833
MHz
ns
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
tCY
HIGH time
tCK-tCLCX
tCK-tCHCX
20
ns
LOW time
ns
RISE time
ns
FALL time
-
20
ns
cycle time (tCY = 12 tCK)
0.75
10
ms
SERIAL PORT CHARACTERISTICS
Serial Port Timing : Shift Register Mode
VDD = 5V±10%;VSS = 0V;Tamb=0°C; Load Capacitance = 80 pF
SYMBOL
PARAMETER
33 MHz OSCILLATOR
UNIT
MIN
360
167
5
MAX
tXLXL
Serial Port clock cycle time
-
ns
ns
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
-
-
0
-
-
167
EXTERNAL CLOCK DRIVE WAVEFORM
VCC-0.5
0.7 VCC
0.2 VCC-0.1
0.45V
TCHCX
TCLCH
TCLCX
TCHCL
TCLCL
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORM
VCC-0.5
VOH-0.1V
VOL+0.1V
VLOAD+0.1V
VLOAD
0.2 VCC+0.9
0.2 VCC-0.1
TIMING REFERENCE
POINTS
0.45V
VLOAD-0.1V
AC Inputs during testing are driven at VCC-0.5V for a
Logic "1" 0.45V for a Logic "0". Timing measurements
are made at VIH min for a Logic "1" and VIL max for a
Logic "0".
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100mV
change form the loaded VOH/VOL level occurs. IOL/IOH = + 20 mA
P/N:PM0803
REV. 0.0, APR. 23, 2001
10
Macronix [ MACRONIX INTERNATIONAL ]
