Step-Down Controllers with
Synchronous Rectifier for CPU Power
These equations are “worst-case” with 45 degrees of
Transformer Design
(MAX796/MAX799 Only)
phase margin to ensure jitter-free fixed-frequency opera-
tion and provide a nicely damped output response for
zero to full-load step changes. Some cost-conscious
designers may wish to bend these rules by using less
expensive (lower quality) capacitors, particularly if the
load lacks large step changes. This practice is tolerable,
provided that some bench testing over temperature is
done to verify acceptable noise and transient response.
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, need a transformer in order to
generate multiple output voltages. The basic electrical
design is a simple task of calculating turns ratios and
adding the power delivered to the secondary in order to
calculate the current-sense resistor and primary induc-
tance. However, extremes of low input-output differen-
tials, widely different output loading levels, and high turns
ratios can complicate the design due to parasitic trans-
former parameters such as inter-winding capacitance,
secondary resistance, and leakage inductance. For
examples of what is possible with real-world transformers,
see the graphs of Maximum Secondary Current vs. Input
Voltage in the Typical Operating Characteristics.
There is no well-defined boundary between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
(usually) harmless jitter is unstable operation, since the
switching frequency is now non-constant. As the
capacitor quality is reduced, the jitter becomes more
pronounced and the load-transient output voltage
waveform starts looking ragged at the edges.
Eventually, the load-transient waveform has enough
ringing on it that the peak noise levels exceed the
allowable output voltage tolerance. Note that even with
zero phase margin and gross instability present, the
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see Inductor L1 for definitions of
parameters). Set the value of the current-sense resistor
at 80mV / I
.
TOTAL
P
= the sum of the output power from all outputs
TOTAL
TOTAL
I
= P
/ V
= the equivalent output cur-
OUT
TOTAL
output voltage noise never gets much worse than I
PEAK
rent referred to V
OUT
x R
(under constant loads, at least).
ESR
V
(V
- V
)
OUT
Designers of RF communicators or other noise-sensi-
tive analog equipment should be conservative and
stick to the guidelines. Designers of notebook comput-
ers and similar commercial-temperature-range digital
OUT IN(MAX)
L(primary) = —————————————
V
x f x I
x LIR
IN(MAX)
TOTAL
V
+ V
SEC
FWD
systems can multiply the R
value by a factor of 1.5
ESR
Turns Ratio N = ——————————————
V
+ V
+ V
OUT(MIN)
RECT SENSE
without hurting stability or transient response.
The output voltage ripple is usually dominated by the
ESR of the filter capacitor and can be approximated as
where: V
is the minimum required rectified sec-
SEC
ondary-output voltage
I
x R
. There is also a capacitive term, so the
RIPPLE
ESR
V
FWD
is the forward drop across the secondary
full equation for ripple in the continuous mode is
rectifier
V
= I x (R + 1 / (2 x pi x f x C )). In
NOISE(p-p)
RIPPLE
ESR
F
V
is the minimum value of the main
OUT(MIN)
idle mode, the inductor current becomes discontinuous
with high peaks and widely spaced pulses, so the
noise can actually be higher at light load compared to
full load. In idle mode, the output ripple can be calcu-
lated as:
output voltage (from the Electrical
Characteristics)
RECT
V
is the on-state voltage drop across the
synchronous-rectifier MOSFET
is the voltage drop across the sense
V
SENSE
resistor
0.02 x R
ESR
V
= —————— +
NOISE(p-p)
In positive-output (MAX796) applications, the trans-
former secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
R
SENSE
0.0003 x L x [1 / V
+ 1 / (V - V
)]
OUT
OUT
IN
———————————————————
2
(R
) x C
F
SENSE
voltage to obtain V
.
SEC
______________________________________________________________________________________ 21
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
