Step-Down Controllers with
Synchronous Rectifier for CPU Power
____________Low-Voltage Operation
__________Applications Information
Low input voltages and low input-output differential volt-
ages each require some extra care in the design. Low
absolute input voltages can cause the VL linear regulator
to enter dropout, and eventually shut itself off. Low input
Heavy-Load Efficiency Considerations
The major efficiency loss mechanisms under loads are,
in the usual order of importance:
2
2
• P(I R), I R losses
voltages relative to the output (low V -V
differential)
IN OUT
can cause bad load regulation in multi-output flyback
• P(gate), gate-charge losses
• P(diode), diode-conduction losses
• P(tran), transition losses
• P(cap), capacitor ESR losses
applications. See the design equations in the Transformer
Design section. Finally, low V -V
differentials can also
IN OUT
cause the output voltage to sag when the load current
changes abruptly. The amplitude of the sag is a function
of inductor value and maximum duty factor (an Electrical
Characteristics parameter, 93% guaranteed over temper-
ature at f = 150kHz) as follows:
• P(IC), losses due to the operating supply current
of the IC
Inductor-core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
2
(I
) x L
STEP
V
SAG
= ———————————————
2 x C x (V
x D
- V
)
OUT
F
IN(MIN)
MAX
The cure for low-voltage sag is to increase the value of
the output capacitor. For example, at V = 5.5V, V
IN
OUT
Efficiency = P
= P
/ P x 100%
IN
OUT
OUT
= 5V, L = 10µH, f = 150kHz, a total capacitance of
660µF will prevent excessive sag. Note that only the
capacitance requirement is increased and the ESR
requirements don’t change. Therefore, the added
capacitance can be supplied by a low-cost bulk
capacitor in parallel with the normal low-ESR capacitor.
/ (P
+ P
) x 100%
OUT
TOTAL
2
P
= P(I R) + P(gate) + P(diode) + P(tran) +
TOTAL
P(cap) + P(IC)
2
2
P(I R) = (I
) x (R
+ R
+ R
SENSE
)
LOAD
DC
DS(ON)
where R
is the DC resistance of the coil, R
is
DC
DS(ON)
is the current-
the MOSFET on-resistance, and R
SENSE
Table 4. Low-Voltage Troubleshooting
SOLUTION
SYMPTOM
CONDITION
ROOT CAUSE
Increase bulk output capacitance per
formula above. Reduce inductor value.
Sag or droop in V
under step load change
Low V -V
<1.5V
differential, Limited inductor-current slew
rate per cycle.
OUT
IN OUT
Dropout voltage is too
Reduce f to 150kHz. Reduce MOSFET
on-resistance and coil DCR.
Low V -V
<1V
differential, Maximum duty-cycle limits
exceeded.
IN OUT
high (V
follows V as
IN
OUT
V
decreases)
IN
Reduce L value. Tolerate the remaining
jitter (extra output capacitance helps
somewhat).
Inherent limitation of fixed-fre-
differential,
Unstable—jitters between Low V -V
IN OUT
quency current-mode SMPS
two distinct duty factors
<1V
slope compensation.
Not enough duty cycle left to
differential,
Reduce f to 150kHz. Reduce secondary
impedances—use Schottky if possible.
Stack secondary winding on main output.
Low V -V
IN OUT
Secondary output won’t
support a load
initiate forward-mode operation.
V
< 1.3 x V
(main)
IN
OUT
Small AC current in primary can’t
store energy for flyback operation.
(MAX796/MAX799 only)
Use a small 20mA Schottky diode for
boost diode D2. Supply VL from an
external source.
VL linear regulator is going into
dropout and isn’t providing
good gate-drive levels.
High supply current,
poor efficiency
Low input voltage, <5V
Won’t start under load or
quits before battery is
completely dead
Supply VL from an external source other
VL output is so low that it hits the
VL UVLO threshold at 4.2V max.
Low input voltage, <4.5V
than V , such as the system 5V supply.
BATT
______________________________________________________________________________________ 23
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
