Step-Down Controllers with
Synchronous Rectifier for CPU Power
sense resistor value. The R
term assumes identi-
ground plane is essential for optimum performance. In
most applications, the circuit will be located on a multi-
layer board and full use of the four or more copper lay-
ers is recommended. Use the top layer for high-current
connections, the bottom layer for quiet connections
(REF, SS, GND), and the inner layers for an uninterrupt-
ed ground plane. Use the following step-by-step guide.
DS(ON)
cal MOSFETs for the high- and low-side switches
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX796 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
qG is twice the data sheet value of an individual MOS-
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
FET. If V
is set to less than 4.5V, replace VL in this
lengths (see Figure 10).
OUT
equation with V
. In this case, efficiency can be
BATT
Priority 2: Minimize ground trace lengths in the
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
high-current paths (discussed below).
Priority 3: Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm max length.
D1 cathode to Q2: 5mm max length
LX node (Q1 source, Q2 drain, D1 cath-
ode, inductor): 15mm max length
P(diode) = diode conduction losses
= I
x V
x t x f
FWD D
LOAD
where t is the diode conduction time (110ns typ) and
D
V
FWD
is the forward voltage of the Schottky.
PD(tran) = transition loss =
Ideally, surface-mount power components are
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
of top-layer copper, so that they don’t go through
vias. The resulting top-layer “sub-ground-plane” is
connected to the normal inner-layer ground plane at
the output ground terminals. This ensures that the
analog GND of the IC is sensing at the output termi-
nals of the supply, without interference from IR
drops and ground noise. Other high-current paths
should also be minimized, but focusing ruthlessly
on short ground and current-sense connections
eliminates about 90% of all PC layout
headaches. See the evaluation kit PC board layouts
for examples.
V
BATT x CRSS
V
x I
LOAD
x f x (——————— + 20ns)
BATT
I
GATE
where C
is the reverse transfer capacitance of the
RSS
high-side MOSFET (a data sheet parameter), I
is
GATE
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver (20ns typ).
2
P(cap) = input capacitor ESR loss = (I
) x R
ESR
RMS
where I
is the input ripple current as calculated in the
Input Capacitor Value section of the Design Procedure.
RMS
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
2) Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive ana-
log components (current-sense traces and REF and
SS capacitors). Placing the IC and analog compo-
nents on the opposite side of the board from the
power-switching node is desirable. Important: the
IC must be no farther than 10mm from the current-
sense resistor. Keep the gate-drive traces (DH, DL,
and BST) shorter than 20mm and route them away
from CSH, CSL, REF, and SS.
2
and I R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
__PC Board Layout Considerations
Good PC board layout is required to achieve specified
noise, efficiency, and stability performance. The PC
board layout artist must be provided with explicit
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX796 and MAX797 EV kit manuals for examples. A
3) Employ a single-point star ground where the input
ground trace, power ground (sub-ground-plane),
and normal ground plane all meet at the output
ground terminal of the supply.
24 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
