Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V 5ꢀ, V
= +2.5V, V
= V
= 0, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
REF
AGND
DGND
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC Glitch Impulse
Major-carry transition
10
nVs
Code = 0000 hex, CS = V
,
DD
Digital Feedthrough
10
nVs
SCLK = V
= 0 to V
levels
DIN
DD
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
BW
Code = FFFF hex
1
1
MHz
mVp-p
dB
Code = 0000 hex, V
= 1Vp-p at 100kHz
REF
SNR
92
75
120
Code = 0000 hex
Code = FFFF hex
Reference Input Capacitance
C
IN
pF
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
2.4
V
V
IH
V
0.8
1
IL
I
IN
V
= 0
µA
pF
V
IN
Input Capacitance
Hysteresis Voltage
POWER SUPPLY
Positive Supply Range
Positive Supply Current
Power Dissipation
C
(Note 6)
10
IN
V
0.40
H
V
DD
4.75
5.25
1.1
V
I
0.3
1.5
mA
mW
DD
PD
TIMING CHARACTERISTICS
(V
= +5V 5ꢀ, V
= +2.5V, V
= V
= 0, CMOS inputs, T = T
to T
, unless otherwise noted.)
MAX
DD
REF
AGND
DGND
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
10
CLK
SCLK Pulse Width High
SCLK Pulse Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
t
45
45
45
45
30
45
40
0
CH
t
CL
ns
t
t
t
ns
CSS0
CSS1
ns
(Note 6)
ns
CSH0
CSH1
t
ns
t
ns
DS
t
ns
DH
V
High to CS Low
DD
20
µs
(power-up delay)
Note 1: Gain Error tested at V
= +2.0V, +2.5V, and +3.0V.
REF
Note 2: R
tolerance is typically 20ꢀ.
OUT
Note 3: Min/Max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8555 hex.
Note 5: Slew-rate value is measured from 0ꢀ to 63ꢀ.
Note 6: Guaranteed by design. Not production tested.
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3
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
