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MAX539BEPA 参数 Datasheet PDF下载

MAX539BEPA图片预览
型号: MAX539BEPA
PDF下载: 下载PDF文件 查看货源
内容描述: + 5V ,低功耗,电压输出,串行12位DAC [+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 16 页 / 208 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,  
S e ria l 1 2 -Bit DACs  
18/MAX539  
nite at code 000 hex. REFIN’s input capacitance is also  
code dependent and has a 50pF maximum value at sever-  
al codes. Because of the code-dependent nature of refer-  
ence input impedances, a high-quality, low-output-imped-  
ance amplifier (such as the MAX480 low-power, precision  
op amp) should be used.  
R
S
REFOUT  
TOTAL  
REFERENCE  
NOISE  
C
S
C
REFOUT  
TEK 7A22  
300  
250  
200  
150  
100  
50  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
If an upgrade to the internal reference is required, the 2.5V  
SINGLE-POLE ROLLOFF  
MAX873A is suitable: ±15mV initial accuracy, TCV  
=
OUT  
7ppm/°C (max).  
C
= 3.3µF  
REFOUT  
Logic Inte rfa c e  
The MAX531/MAX538/MAX539 logic inputs are designed to  
be compatible with TTL or CMOS logic levels. However, to  
achieve the lowest power dissipation, drive the digital inputs  
with rail-to-rail CMOS logic. With TTL logic levels, the power  
requirement increases by a factor of approximately 2.  
0.6  
0.4  
0.2  
0
C
= 47µF  
REFOUT  
Se ria l Cloc k a nd Upda te Ra te  
0
Figure 1 shows the MAX531/MAX538/MAX539 timing. The  
0.1  
1
10  
100  
1000  
maximum serial clock rate is given by 1 / (t  
+ t ),  
CH  
CL  
FREQUENCY (kHz)  
approximately 14MHz. The digital update rate is limited by  
the chip-select period, which is 16 x (t + t ) + t  
.
CSW  
CH  
CL  
Figure 2. Reference Noise vs. Frequency  
This equals a 1.14µs, or 877kHz, update rate. However, the  
DAC settling time to 12 bits is 25µs, which may limit the  
update rate to 40kHz for full-scale step transitions.  
Inte rna l Re fe re nc e (MAX531 only)  
The on-chip reference is lesser trimmed to generate 2.048V  
at REFOUT. The output stage can source and sink current,  
so REFOUT can settle to the correct voltage quickly in  
response to code-dependent loading changes. Typically,  
source current is 5mA and sink current is 100µA.  
____________Applic a tions Inform a tion  
Refer to Figures 3a and 3b for typical operating connec-  
tions.  
Se ria l Inte rfa c e  
REFOUT connects the internal reference to the R-2R DAC  
ladder at REFIN. The R-2R ladder draws 50µA maximum  
load current. If any other connection is made to REFOUT,  
ensure that the total load current is less than 100µA to  
avoid gain errors.  
The MAX531/MAX538/MAX539 use a three-wire serial  
inte rfa c e tha t is c omp a tib le with SPI™, QSPI™  
(CPOL = CPHA = 0), and Microwire™ standards as shown  
in Figures 4 and 5. The DAC is programmed by writing two  
8-bit words (see Figure 1 and the Functional Diagram).  
Sixteen bits of serial data are clocked into the DAC MSB  
first with the MSB preceded by four fill (dummy) bits. The  
four dummy bits are not normally needed. They are  
required only when DACs are daisy-chained. Data is  
clocked in on SCLK’s rising edge while CS is low. The seri-  
al input data is held in a 16-bit serial shift register. On CSs  
rising edge, the 12 least significant bits are transferred to  
the DAC register and update the DAC. With CS high, data  
cannot be clocked into the MAX531/MAX538/MAX539.  
For applications requiring very low-noise performance,  
connect a 33µF capacitor from REFOUT to AGND. If noise  
is not a concern, a lower value capacitor (3.3µF min) may  
be used. To reduce noise further, insert a buffered RC filter  
between REFOUT and REFIN (Figure 2). The reference  
bypass capacitor, C , is still required for reference  
REFOUT  
stability. In applications not requiring the reference, con-  
nect REFOUT to V or use the MAX538 or MAX539 (no  
DD  
internal reference).  
Exte rna l Re fe re nc e  
The MAX531/MAX538/MAX539 input data in 16-bit blocks.  
The SPI and Microwire interfaces output data in 8-bit  
blocks, thereby requiring two write cycles to input data to  
the DAC. The QSPI interface allows variable data input  
from eight to 16 bits, and can be loaded into the DAC in  
one write cycle.  
An external reference in the range (V + 2V) to (V - 2V)  
SS  
DD  
may be used with the MAX531 in dual-supply operation.  
With the MAX538/MAX539 or the MAX531 in single-supply  
use, the reference must be positive and may not exceed  
V
DD  
- 2V. The reference voltage determines the DACs full-  
scale output. The DAC input resistance is code dependent  
and is minimum (40k) at code 555 hex and virtually infi-  
SPI and QSPI are trademarks of Motorola, Inc.  
Microwire is a trademark of National Semiconductor Corp.  
_______________________________________________________________________________________  
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