Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
ELECTRICAL CHARACTERISTICS—MAX5154 (continued)
(V = +5V ±10%, V
= V
= 2.048V, R = 10kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical values are
DD
REFA
REFB
L
L
A
MIN
MAX
at T = +25°C (OS_ tied to AGND for a gain of +2V/V).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.40
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.75
15
V/µs
µs
To 1/2LSB of full-scale, V
= 4V
STEP
Output Voltage Swing
OSA or OSB Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
Rail-to-rail (Note 2)
0 to V
V
DD
R
24
34
25
5
kΩ
µs
OS_
nV-s
nV-s
CS = V , f
= 100kHz, V
= 5Vp-p
DD DIN
SCLK
Digital Crosstalk
5
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
Power-Supply Current
V
4.5
5.5
V
DD
I
DD
(Note 3)
(Note 3)
0.5
2
0.65
mA
I
10
±1
µA
µA
DD(SHDN)
in Shutdown
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
0
t
CP
(Note 4)
100
40
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise
Setup Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise
Hold Time
t
CSH
SDI Setup Time
SDI Hold Time
t
40
0
ns
ns
DS
t
DH
SCLK Rise to DOUT
Valid Propagation Delay
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT
Valid Propagation Delay
t
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
t
CS1
t
100
CSW
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for V _ greater than 6mV and less than V - 50mV. Guaranteed by PSRR test at the end
OUT
DD
points.
Note 3: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
Note 4: SCLK minimum clock period includes the rise and fall times.
_______________________________________________________________________________________
3
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
