+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs in QS OP -1 6
CS
1
8
1
8
1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
DOUT
SSTRB
Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
SCLK
8/MAX1249
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6
CONVERSION RESULT 1
Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current typically
to 2µA. Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30µA. Power-up time can be
shortened to 5µs in internal compensation mode.
Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The
Typical Operating Circuit uses a 4.7µF capacitor at
VREF. A value of 4.7µF or greater ensures reference-
buffer stability and allows converter operation at the
2MHz full clock speed. External compensation increas-
es power-up time (see Choosing Power-Down Mode
and Table 4).
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 11a and 11b show
the various power-down sequences in both external and
internal clock modes.
Pull SHDN hig h to s e le c t inte rna l c omp e ns a tion.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Ch o o s in g P o w e r-Do w n Mo d e
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down or fast power-down mode via bits 1 and 0
of the DIN c ontrol b yte with SHDN hig h or floa ting
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
