+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs in QS OP -1 6
8/MAX1249
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
SSTRB
DOUT
START
RB2
B6
RB3
RB1
FILLED WITH
ZEROS
B9
MSB
B0
LSB
B8
B7
B5
B4
B3
B2
B1
S1
S0
ACQUISITION
1.5µs
CONVERSION
A/D STATE
IDLE
IDLE
(f
CLK
= 2MHz)
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
≤ 2MHz)
SCLK
• • •
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
t
t
TR
DV
DO
DOUT
• • •
Figure 6. Detailed Serial-Interface Timing
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or d roop on the s a mp le -a nd -hold c a p a c itors ma y
degrade conversion results. Use internal clock mode if
______________________________________________________________________________________ 11
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
