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MAX125CEAX 参数 Datasheet PDF下载

MAX125CEAX图片预览
型号: MAX125CEAX
PDF下载: 下载PDF文件 查看货源
内容描述: 2X4通道,同时采样,14位DAS [2x4-Channel, Simultaneous-Sampling 14-Bit DAS]
分类和应用:
文件页数/大小: 24 页 / 243 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,  
S e ria l 1 0 -Bit ADCs in QS OP -1 6  
8/MAX1249  
Most microcontrollers require that conversions occur in  
multiples of 8 SCLK clocks; 16 clocks per conversion is  
typically the fastest that a microcontroller can drive the  
MAX1248/MAX1249. Figure 10b shows the serial-inter-  
face timing necessary to perform a conversion every 16  
SCLK cycles in external clock mode.  
Da t a Fra m in g  
The falling edge of CS does not start a conversion. The  
first logic high clocked into DIN is interpreted as a start  
bit and defines the first bit of the control byte. A conver-  
sion starts on the falling edge of SCLK, after the eighth  
bit of the control byte (the PD0 bit) is clocked into DIN.  
The start bit is defined as:  
__________ Ap p lic a t io n s In fo rm a t io n  
The first high bit clocked into DIN with CS low any  
time the converter is idle; e.g., after V is applied.  
DD  
P o w e r-On Re s e t  
When power is first applied, and if SHDN is not pulled  
low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the  
MAX1248/MAX1249 in internal clock mode, ready to  
convert with SSTRB = high. After the power supplies  
have stabilized, the internal reset time is 10µs, and no  
conversions should be performed during this phase.  
SSTRB is high on power-up and, if CS is low, the first  
logical 1 on DIN is interpreted as a start bit. Until a con-  
version takes place, DOUT shifts out zeros (also see  
Table 4).  
OR  
The first high bit clocked into DIN after bit 3 of a con-  
version in progress is clocked onto the DOUT pin.  
If CS is toggled before the current conversion is com-  
plete, the next high bit clocked into DIN is recognized as  
a start bit; the current conversion is terminated, and a  
new one is started.  
The fastest the MAX1248/MAX1249 can run with CS  
held low between conversions is 15 clocks per conver-  
sion. Figure 10a shows the serial-interface timing nec-  
essary to perform a conversion every 15 SCLK cycles  
in external clock mode. If CS is tied low and SCLK is  
continuous, guarantee a start bit by first clocking in 16  
zeros.  
Re fe re n c e -Bu ffe r Co m p e n s a t io n  
In addition to its shutdown function, SHDN selects inter-  
na l or e xte rna l c omp e ns a tion. The c omp e ns a tion  
affects both power-up time and maximum conversion  
speed. The 100kHz minimum clock rate is limited by  
droop on the sample-and-hold, and is independent of  
the compensation used.  
CS  
• • •  
t
CONV  
t
CSS  
t
t
SCK  
CSH  
SSTRB  
SCLK  
• • •  
t
SSTRB  
• • •  
t
DO  
PD0 CLOCK IN  
DOUT  
• • •  
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.  
Figure 9. Internal Clock Mode SSTRB Detailed Timing  
______________________________________________________________________________________ 13