+2 .7 V t o +5 .2 5 V, Lo w -P o w e r, 4 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs in QS OP -1 6
DIF
Table 2. Channel Selection in Single-Ended Mode (SGL/
= 1)
SEL2
0
SEL1
0
SEL0
1
CH0
CH1
CH2
CH3
COM
+
–
1
0
1
0
1
1
1
0
0
+
–
–
–
+
+
DIF
Table 3. Channel Selection in Differential Mode (SGL/
= 0)
SEL2
0
SEL1
0
SEL0
1
CH0
CH1
CH2
CH3
+
–
0
1
1
1
0
1
0
1
0
+
–
–
+
–
+
8/MAX1249
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
10-bit conversion result). See Figure 19 for MAX1248/
MAX1249 QSPI connections.
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 16). For bipolar inputs, the output is two’s com-
plement (Figure 17). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
Clo c k Mo d e s
The MAX1248/MAX1249 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the e xte rna l c loc k s hifts d a ta in a nd out of the
MAX1248/MAX1249. The T/H acquires the input signal
as the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 6–9 show the timing characteristics
common to both modes.
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 10 SCLK falling edges (Figure 5).
SSTRB and DOUT go into a high-impedance state when
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two sub-bits, and three trailing
zeros. The total conversion time is a function of the
10 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
