MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 3Msps, f
= 48MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
Input Hysteresis
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OVDD
V
mV
HYST
O0.15
0.09
3
Input Leakage Current
I
V
= 0V or V
1.0
FA
IN
AIN_
DD
Input Capacitance
C
pF
IN
DIGITAL OUTPUTS (DOUT, EOC)
V
OVDD
Output Voltage Low
Output Voltage High
V
I
I
= 200FA
V
V
OL
SINK
O0.15
V
OVDD
V
= 200FA
SOURCE
OH
O0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
-0.3
4
1.5
FA
CS = V
CS = V
L
DD
C
pF
OUT
DD
V
2.35
1.5
3.0
3.0
5.1
2.5
3.6
3.6
6.5
V
V
DD
Digital I/O Supply Voltage
V
OVDD
f
f
= 3Msps
SAMPLE
SAMPLE
Positive Supply Current
I
= 0Msps (3Msps devices)
mA
DD
Full shutdown
0.0013 0.006
V
= 3V,
DD
15.2
Normal mode
(external
reference)
f
= 3Msps
SAMPLE
V
= 2.35V,
DD
10.3
7.3
f
= 3Msps
SAMPLE
mW
V
= 3V,
DD
Power Dissipation
f
= 3Msps
SAMPLE
AutoStandby
V
= 2.35V,
DD
4.35
f
= 3Msps
SAMPLE
V
= 3V
3.9
1.7
Full/
AutoShutdown
DD
DD
FW
V
= 2.35V
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
20.8
40
4
ns
%
CP
CH
t
60
16.5
15
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
C
10pF
=
OVDD
LOAD
SCLK Fall to DOUT Transition
t
ns
DOT
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
t
14
DOE
t
4
DS
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7
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