DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
—
SYMBOL POSITION
NAME AND DESCRIPTION
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position;
set to zero to force RLCLK low during Sa8 bit position. See Section 18.1
for timing details.
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RCR2.7
RCR2.6
RCR2.5
RCR2.4
RCR2.3
RCR2.2
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit position;
set to zero to force RLCLK low during Sa7 bit position. See Section 18.1
for timing details.
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit position;
set to zero to force RLCLK low during Sa6 bit position. See Section 18.1
for timing details.
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit position;
set to zero to force RLCLK low during Sa5 bit position. See Section 18.1
for timing details.
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit position;
set to zero to force RLCLK low during Sa4 bit position. See Section 18.1
for timing details.
Receive-Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048/4.096/8.192 MHz
Receive-Side Elastic Store Enable.
RESE
—
RCR2.1
RCR2.0
0 = elastic store is bypassed
1 = elastic store is enabled
Not Assigned. Should be set to zero when written.
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