DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)
(MSB)
(LSB)
FLB
THDB3
TG802
TCRC4
RSM
RHDB3
RG802
RCRC4
SYMBOL POSITION
NAME AND DESCRIPTION
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
FLB
CCR1.7
CCR1.6
CCR1.5
CCR1.4
CCR1.3
CCR1.2
CCR1.1
CCR1.0
Transmit HDB3 Enable.
THDB3
TG802
TCRC4
RSM
0 = HDB3 disabled
1 = HDB3 enabled
Transmit G.802 Enable. See Section 18 for details.
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
Transmit CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
Receive Signaling Mode Select.
0 = CAS signaling mode
1 = CCS signaling mode
Receive HDB3 Enable.
RHDB3
RG802
RCRC4
0 = HDB3 disabled
1 = HDB3 enabled
Receive G.802 Enable. See Section 18 for details.
0 = do not force RCHBLK high during bit 1 of time slot 26
1=force RCHBLK high during bit 1 of time slot 26
Receive CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
5.3. Framer Loopback
When CCR1.7 is set to one, the DS21354/DS21554 enter a framer loopback (FLB) mode. See Figure 2-1
for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted as normal at TPOSO and TNEGO.
2) Data input via RPOSI and RNEGI will be ignored.
3) The RCLK output will be replaced with the TCLK input.
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