DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(LSB)
ID0
(MSB)
T1E1
Bit 6
Bit 5
Bit 4
ID3
ID2
ID1
SYMBOL POSITION
NAME AND DESCRIPTION
T1 or E1 Chip Determination Bit. Set to 1.
0 = T1 chip
T1E1
IDR.7
1 = E1 chip
Bit 6
Bit 5
Bit 4
IDR.6
IDR.5
IDR.4
Bit 6. See Table 5-1.
Bit 5. See Table 5-1.
Bit 4. See Table 5-1.
Chip Revision Bit 3. MSB of a decimal code that represents the chip
ID3
IDR.3
revision.
ID2
ID1
IDR.1
IDR.2
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents the chip
ID0
IDR.0
revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
—
—
FRC
SYNCE
RESYNC
SYMBOL POSITION
NAME AND DESCRIPTION
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSYNC Mode Select.
RSMF
RCR1.7
RSM
RSIO
RCR1.6
RCR1.5
0 = frame mode (see the timing in Section 18)
1 = multiframe mode (see the timing in Section 18)
RSYNC I/O Select. (Note: this bit must be set to zero when RCR2.1=0).
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Frame Resync Criteria.
—
—
RCR1.4
RCR1.3
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three
consecutive times
FRC
RCR1.2
Sync Enable.
SYNCE
RCR1.1
RCR1.0
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resync is initiated. Must be
cleared and set again for a subsequent resync.
RESYNC
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